Shift registers constructed by serially coupling a plurality of charge cells in cascade to form an array are known in the art. Charge is typically transferred from cell to cell in the array in response to clock signals applied to cells of the array.
A received charge can be split among several cells by coupling a plurality of cells to receive the charge and simultaneously clocking selected cells into a charge receiving state.
With such an approach, the splitting ratio is influenced by the cell gate areas. If charge is to be split into two halves, for example, the charge receiving cells should have identical gate areas. Splitting inaccuracy results if the areas are mismatched. The split charges can be expressed as follows:
Charge in cell A = pQ =(Q/2)(1 - .epsilon.) PA1 Charge in cell B = rQ = (Q/2)(1 + .epsilon.),
where .epsilon. represents a splitting error caused, for example, by layout or processing.
An improved charge splitting device made in accordance with the invention brings a quantity of charge Q into a splitting cell and splits the charge Q into two charge portions pQ and rQ, p and Q being splitting coefficients where p = 1/2(1 - .epsilon.) and r = 1/2(1 + .epsilon. ), .epsilon. being the error in charge splitting. The charge portion rQ is stored and the charge portion pQ is again divided by splitting cell into charge portions p.sup.2 Q and prQ. The charge portion prQ is equal to (Q/4)(1 - .epsilon..sup.2). The charge portions p.sup.2 Q and r.sup.2 Q are summed to produce the quantity (Q/2)(1 + .epsilon..sup.2). The charge portions (Q/4)(1 - .epsilon..sup.2) and (Q/2)(1 + .epsilon..sup.2) are more highly accurate representations of Q/4 and Q/2 than representations heretofore available by devices having an .epsilon. &lt; 1.